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TGF4230-EEU
1.2mm Discrete HFET
q q q q q q
PHOTO ENLARGEMENT
1200 m X 0.5 m HFET Nominal Pout of 28.5- dBm at 8.5- GHz Nominal Gain of 10.0- dB at 8.5- GHz Nominal PAE of 55% at 8.5 - GHz
4230
Suitable for High-Reliability Applications 0,572 x 0,699 x 0,102 mm (0.023 x 0.028 x 0.004 in.)
DESCRIPTION
The Triquint TGF4230 - EEU is a single gate 1.2 mm Discrete GaAs Heterostructure Field Ef fect Transistor (HFET) designed for high- efficiency power applications up to 1 2- GHz in Class A and Class AB operation. Bond - pad and backside metalization is gold plated for compatibility with eutectic alloy attach methods as well as thermocompression and thermosonic wire- bonding processes. The TGF4230-EEU is readily assembled using automatic equipment.
TriQuint Semiconductor, Inc.
*
Texas Facilities
* (972) 995-8465
* www.triquint.com
TGF4230-EEU
EXAMPLE OF DC I-V CURVES
0.3 VG = 0.0 to -2.25 V (0.25 V steps) C TA = 25
0.25
Drain Current (A)
0.2
0.15
0.1
0.05
0 0 1 2 3 4 5 6 7 8 9 10
Drain Voltage (V)
OUTPUT POWER VS. INPUT POWER Output Power (dBm)
30 28
26 24
F = 8.5GHz V D =8.0V I Q =50mA* C T A =25
22 20 18 16 4 6 8 10 12 14 16 18 20 22
Input Power (dBm) Note: I Q is defined as the drain current before application of RF signal at the input.
POWER ADDED EFFICIENCY VS. INPUT POWER
60
55 50
45 40
F = 8.5GHz V D =8.0V I Q =50mA* C T A =25
PAE (%)
35 30 25 20 15
10 5 4 6 8 10 12 14 16 18 20 22
Input Power (dBm)
2
TriQuint Semiconductor, Inc.
*
Texas Facilities
* (972) 995-8465
* www.triquint.com
TGF4230-EEU
GAIN VS. INPUT POWER
12
11
F =8.5GHz V D =8.0V I Q =50mA* C T A =25
Gain (dB)
10
9
8
7 4 6 8 10 12 14 16 18 20 22
Input Power (dBm)
DRAIN CURRENT VS. INPUT POWER Drain Current (mA)
180 160 140 120
F =8.5GHz V D =8.0V I Q =50mA* C T A =25
100
80
60 40 4 6 8 10 12 14 16 18 20 22
Input Power (dBm)
ABSOLUTE MAXIMUM RATINGS
. Drain - to- source Voltage, VDS ................................................................................................................ 12 V Gate - to- source Voltage, V ...................................................................................................... - 5 V to 0 V GS Mounting temperatur e (30 sec), TM .................................................................................................. 320 C Storage temperature range, TSTG ............................................................ ................................ - 65 to 200 C Power dissipation, PD .................................................................................. (see thermal data on next page) Operating channel temperature, T CH .............................................................. (see thermal data on next page)
Ratings over base-plate temperature range T BP (unless otherwise noted)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated "RF and DC Characteristics" is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
TriQuint Semiconductor, Inc.
*
Texas Facilities
* (972) 995-8465
* www.triquint.com
3
TGF4230-EEU
p PREDICTED CHANNEL TEMPERA TURE VS. BASE TEMPERA TURE at 0.51 W and 1.02 W dissipated power
300
Channel Temperature ( C)
250 200 150
100 50 0 -50 -100 -100 -50 0 50 100 150 200
0.51 W (soldered to carrier) 0.51 W (HFET backside metal) 1.02 W (soldered to carrier) 1.02 W (HFET backside metal)
Base Temperature ( C) Case 1: Base temperature at backside of carrier (with 38 m AuSn solder attach to 0.5 mm CuMo Car rier). Case 2: Base temperature at backside of 1.2 mm HFET .
p HFET CHANNEL TEMPERATURE VS. MEDIAN LIFE
325 300
Channel Temperature ( C)
275
250
225 200
175 150 125 100 1 2 3 4 5 6 7 8
11415 years
9
10
Median Life (10^X Hours)
4
TriQuint Semiconductor, Inc.
*
Texas Facilities
* (972) 995-8465
* www.triquint.com
TGF4230-EEU
RF AND DC CHARACTERISTICS Pout GP PAE I DSS GM VP BV G S BV G D
PARAMETER
MIN
NOMINAL
MAX
UNIT
Output Power Power Gain Power Added Efficiency Drain Saturation Current Transconductance Pinch Off Voltage Breakdown Voltage Gate-Source Breakdown Voltage Gate-Drain
27.5 8 50 204 144 -2.7 -30 -30
28.5 10 55 294 198 -1.85 -22 -22
384 252 -1 -17 -17
dBm dB % mA mS V V V
Pout, Gain, and P AE: Measured at 8.5 GHz, drain voltage of 8.0 V . Gate voltage is adjusted to achieve quiescent current of approximately 20% I DSS with no RF signal applied. The source is gr ounded. Input power between 18 and 19-dBm. IDSS: Saturated drain-source current. Sear ch for the maximum IDS at VGS = 0.0 V, and VDS swept between 0.5 V to 3.5 V. Note that the drain voltage at which I DSS is located and recorded as VDSP. GM: Transconductance. (I DSS - I DS1 )/ I VG1 I. I DS1 measured at VG1 = -0.25 V using the knee search technique; VDS swept between 0.5 V and VDSP to search for maximum I DS1. VP: Pinch off voltage. VGS for I DS = 0.5 mA/mm of gate width. V DS fixed at 2.0 V, VGS swept to bring I DS to 0.5 mA/mm. Sweep will stop if V P current not found beyond 0.5 V of the minimum V P specification. BVGS: Breakdown voltage, gate to source. I BD = 1.0 mA/mm of gate width. Source fixed at ground, drain not connected (floating). When 1.0mA/mm drawn at gate, V GS measured as B VGS. BVGD: Breakdown voltage, gate to drain. I BD = 1.0 mA/mm of gate width. Drain fixed at gr ound, source not connected (floating). When 1.0 mA/mm drawn at the gate, V GD measured as B VGD.
LINEAR MODEL
R DG LG G RI R GS C GS R1 RG
C DG
V CCS
RD
LD D
C DS R2 R DS
RS
LS
VDS = 8.0 V and 30% I DSS at T = 25C
FET Elements
L G = 0.0421 nH R G = 0.43 R G S = 81700 R I = 1.21 C GS = 1.21 pF C DG = 0.1004 pF
R DG = 204000 RS = 0.4 L S = 0.015 nH R DS = 98.01 CDS = 0.25325 pF R D = 0.66 L D = 0.022 nH
VCCS Parameters
M = 132.9 mS A=0 R1 = 1E19 R2 = 1E19 F=0 T = 5.49 pS
5
TriQuint Semiconductor, Inc.
*
Texas Facilities
* (972) 995-8465
* www.triquint.com
TGF4230-EEU
MODELED S-PARAMETERS
Frequency (GHz) MAG
S 11 ANG(o) MAG
S 21 ANG(o) MAG
S 12 ANG(o) MAG
S 22 ANG(o)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
0.985 0.959 0.931 0.908 0.891 0.880 0.871 0.865 0.861 0.858 0.856 0.855 0.854 0.854 0.854 0.855 0.855 0.856 0.857 0.858 0.859 0.860 0.862 0.863 0.864 0.866 0.867 0.869
-29.88 -56.20 -77.47 -94.02 -106.82 -116.82 -124.76 -131.19 -136.48 -140.92 -144.69 -147.94 -150.78 -153.29 -155.53 -157.54 -159.37 -161.04 -162.58 -164.01 -165.34 -166.58 -167.76 -168.87 -169.93 -170.94 -171.91 -172.84
8.095 7.297 6.368 5.512 4.791 4.202 3.723 3.330 3.004 2.732 2.501 2.304 2.133 1.984 1.852 1.736 1.632 1.539 1.455 1.378 1.308 1.244 1.186 1.131 1.081 1.034 0.991 0.950
161.49 145.18 131.86 121.22 112.62 105.49 99.42 94.11 89.37 85.06 81.09 77.39 73.90 70.59 67.43 64.40 61.49 58.67 55.95 53.30 50.73 48.23 45.79 43.41 41.09 38.83 36.62 34.46
0.021 0.038 0.050 0.057 0.062 0.065 0.067 0.068 0.069 0.069 0.069 0.068 0.068 0.067 0.066 0.065 0.065 0.064 0.063 0.061 0.060 0.059 0.058 0.057 0.056 0.055 0.053 0.052
72.66 58.80 47.65 39.12 32.60 27.55 23.56 20.34 17.70 15.51 13.67 12.12 10.82 9.72 8.80 8.05 7.45 7.00 6.68 6.49 6.43 6.51 6.71 7.05 7.52 8.12 8.86 9.74
0.343 0.328 0.312 0.301 0.295 0.294 0.297 0.302 0.309 0.319 0.329 0.340 0.352 0.364 0.377 0.390 0.404 0.417 0.430 0.444 0.457 0.470 0.483 0.496 0.509 0.521 0.534 0.546
-22.22 -41.75 -57.46 -69.57 -78.80 -85.89 -91.41 -95.80 -99.38 -102.37 -104.94 -107.18 -109.19 -111.03 -112.73 -114.32 -115.84 -117.29 -118.68 -120.03 -121.35 -122.63 -123.89 -125.11 -126.32 -127.51 -128.68 -129.82
VDS = 8.0 V and 30% I DSS at T = 25C
6
TriQuint Semiconductor, Inc.
*
Texas Facilities
* (972) 995-8465
* www.triquint.com
TGF4230-EEU
MECHANICAL DRAWING
0.699
0.601
2
R/C**
0.350
1
4
0.099
3
0.0 0.0 0.097 0.264 0.471 0.572
Units: Millimeters Thickness: 0.102 Chip size 0.0508
Bond Bond Bond Bond
pad pad pad pad
1 2 3 4
(gate): 0.072 x 0.075 (gate): 0.075 x 0.075* (gate): 0.075 x 0.075* (drain): 0.083 x 0.077
Minimum connections to Bond Pads 1 and 4. Sources are connected to backside metalization. * Alternate gate pads used for paralleling TGF4230s or for multiple gate wir es. ** Wafer unique Row/Column data is recorded in brackets.
NOTES
Gate bias supplies should be designed to sink or source gate current. The magnitude and direction of the gate current is a function of bias point, load impedance, and drive level.
7
TriQuint Semiconductor, Inc.
*
Texas Facilities
* (972) 995-8465
* www.triquint.com

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